1. Field of the Invention
The present invention relates to a reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories.
2. Discussion of the Related Art
In non-volatile memories, such as for example EPROMs, EEPROMs, and FLASH memories, each memory cell can be in only one of two possible conditions: programmed or non-programmed (virgin). Conductivity characteristics of the memory cells are related to these two conditions.
There are no intermediate conditions of the memory cells with conductivity characteristics interpolated between a conductivity level of a programmed cell and that of a non-programmed cell, so as to be able to use this intermediate conductivity as a reference to determine whether a particular memory cell is programmed or non-programmed. Therefore, it is necessary to plot a curve for distinguishing between the two conductivity levels of the memory cell. Various circuital techniques, developed to provide a reference that allows one to determine the status of a memory cell, are commonly known.
The two most common systems are the current mirroring system, with a 2:1 and 3:1 ratio, and the so-called "current offset" system; these systems are shown in FIG. 1 (with details in FIGS. 2 and 3) and in FIG. 4. The charts with the conductivity curves related to these systems are shown, for the sake of reference, respectively in FIGS. 25 and 26.
FIG. 1 illustrates a current mirroring system with a 2:1 ratio, characterized by a circuit that includes a first branch, or matrix branch, and a second branch, or reference branch. The first branch connects a load 1 to a matrix of memory cells from which, by a multiplexer selection circuit YM and YN, a memory cell 4 of the memory matrix is selected. The second branch connects a load 1' to a matrix of virgin reference memory cells, from which one virgin reference memory cell 4' is selected by multiplexer selection circuit YM, YN. Transistors 2 and 2' enable the flow current from the loads 1 and 1' to the memory cells 4 and 4' and are arranged in the first branch, and in the second branch respectively. Biasing structures 3 and 3' are provided to bias the transistors 2 and 2', respectively.
FIG. 2 shows, in more detail, the loads 1 and 1', in the case of a 2:1 current mirroring ratio, wherein the load 1 is constituted by a single transistor and the load 1' is constituted by two transistors. The current of the reference memory cell 4', designated by Icell, is mirrored in the load transistors and a current equal to Icell/2 flows in the first branch.
If the memory cell 4 is virgin (like the reference memory cell 4' in which the current Icell flows), an output node provided on the matrix branch becomes low, since the load does not deliver the current that the reference memory cell 4' allows to pass, i.e, Icell. The load 1 in fact delivers only the current Icell/2.
If instead the memory cell 4 is programmed (i.e., off), the output node of the matrix branch becomes high, since even if the current Icell/2 is weak, it causes the node to become high, since the memory cell 4 is off because it is programmed.
This characteristic can be defined by a conductivity curve for the memory cell 4, to be compared with a conductivity curve of the virgin reference memory cell 4'.
In summary, therefore, if a current Im on the matrix branch is Im=0 (the cell is off and programmed), a current on the reference branch Ir is equal to 1/2 a current Iv of the virgin memory cell 4' for each mirroring transistor. When balancing occurs, if Im=1/2 Iv and Ir=1/2 Iv, then the state of the memory cell 4 cannot be determined. Finally, if the memory cell 4 is virgin (Im=Iv), then the current on the reference branch is Ir=Iv/2.
FIG. 3 shows in detail the loads 1 and 1' in the case of a 3:1 mirroring ratio, in which the load 1 is again constituted by a single transistor, whereas the load 1' is constituted by three transistors. The cell current, designated by Icell, is mirrored in the load transistors, and a current equal to Icell/3 flows in the matrix branch.
As in the previous case, the following relations occur in the case of a memory cell when it is programmed, when balancing occurs, and when it is virgin:
______________________________________ programmed: Im = 0 Ir = 1/3Iv for each mirroring transistor balanced: Im = 1/3Iv Ir = 1/3Iv for each mirroring transistor virgin: Im = Iv Ir = 1/3Iv for each mirroring transistor ______________________________________
The purpose of the circuit shown in FIG. 1 is to create a curve of the conductivity of a reference memory cell 4' as a function of the voltage. In this manner it is possible to compare the conductivity curve of the memory cell 4 whose status must be determined with respect to the reference curve.
Therefore, if one finds that the examined memory cell 4 allows the same current as a reference cell to pass, then it is a virgin cell; otherwise it is a programmed cell.
The reference curve thus created has the drawback that for low voltage values it has very low current difference values with respect to the actual conductivity curves of memory cells and therefore accurate determination of their status is difficult.
Furthermore, for high voltage values, the reference curve and the conductivity curve intersect, causing incorrect cell status determination.
The 3:1 mirroring circuit allows one to plot another conductivity curve that is lower than the first one so as to more assuredly detect the status of a cell that might be only weakly programmed and which cannot be determined with the first above mentioned reference curve.
This last curve allows one to provide a "margin" for reading during a verify step after programming, in order to ensure the normal reading that is performed with a 2:1 ratio.
The chart of the curves of this first reference system is shown in FIG. 25.
FIG. 4 shows a so-called "current offset" reference system, in which current mirroring is performed at the level of the bit lines.
The drawbacks of these known reference systems are the poor symmetry of the loads, the difficulty in biasing propagation, and higher current consumption caused by the current offset.
The chart with the curves of this reference system is shown in FIG. 26.
A lack of symmetry at the loads is a problem when using sense amplifiers of the dynamic latch type that require perfect balancing.
Furthermore, the vector of the current difference between the matrix current and the current of the reference branch, Im-Ir, in the most favorable conditions, is never higher than Iv/2.
Another drawback is due to the fact that both of the reference systems are difficult to implement in architectures in which the roles of the reference and matrix branches are reversed.